Preliminary calendar, subject to change!

Calendar

The Hardware Software Interface

Jan 21

Intro & What is Computer Architecture? [slides] [pdf]

Syllabus

Jan 22

No Lab

Jan 23

(re-)Introducing the HW-SW Interface [slides] [pdf]

H&P 1.3, 1.9

Jan 26

Data Representations & Assembly [slides] [pdf]

H&P A.1, A.2

Jan 28

Designing an Assembly Instruction [slides] [pdf]

S&L 1.2

Jan 29

Assembly Lab

Jan 30

Assembly Design, cont. [slides] [pdf]

H&P A.4, A.7 Check-In 1 in class HW1 Released

Feb 2

RISC v CISC [slides] [pdf]

TCftRISC

Last Day to Add Course!

Basic Processor Design

Feb 4

Hardware Principles [slides] [pdf]

TBD

Feb 5

Processor Emulator Gear-Up Lab

Feb 6

Building a Basic Processor (Part 1) [slides] [pdf]

TBD HW1 Part 1 due Tonight!

Feb 9

Building a Basic Processor (Part 2) [slides] [pdf]

TBD

Feb 11

Single Cycle Processor Control and Performance [slides] [pdf]

TBD

Feb 12

GDB Lab

Feb 13

Building a Pipelined CPU [slides] [pdf]

TBD Check-In 2 in class

Feb 16

Pipelined Processor (Part 2) [slides] [pdf]

TBD HW1 Part 2 due Tonight!

Feb 18

Pipeline Pitfalls and Hazards [slides] [pdf]

TBD

Feb 19

Intro to gem5 Lab

Feb 20

Managing Hazards [slides] [pdf]

TBD

Feb 23

Introducing Processor Control [slides] [pdf]

TBD

Memory Hierarchy

Feb 25

Memory Hierarchy Overview [slides] [pdf]

TBD HW1 Part 3 due Tonight! HW2 released

Feb 26

Cache Assignment Gear-Up Lab

Feb 27

No class!

Mar 2

Storage Devices [slides] [pdf]

TBD Check-In 3 in class

Mar 4

Cache Controller Construction [slides] [pdf]

TBD

Mar 5

Cache Performance Lab

Mar 6

Understanding and Mitigating Misses [slides] [pdf]

TBD

Mar 9

Coherence and Shared Caches [slides] [pdf]

TBD

Mar 11

Memory System Performance and Revisiting the Memory Wall [slides] [pdf]

TBD

Mar 12

HW2 Office Hours (Optional)

Today is the last day to drop course!

Mar 13

Cache Security and Mitigations [slides] [pdf]

TBD Check-In 4 In-class

Mar 16

No class, spring break!

Mar 18

No class, spring break!

Mar 20

No class, spring break!

Mar 23

Cache Attacks [slides] [pdf]

TBD HW3 Released

Mar 25

Cache Attack Mitigations [slides] [pdf]

TBD

Mar 26

ISA Leakage Gear-Up

Mar 27

No class (Farmworkers Day)!

Advanced Processing (Control Instructions)

Mar 30

Basic Control Instructions [slides] [pdf]

TBD

Apr 1

Constructing a Data path for Control Instructions [slides] [pdf]

TBD HW3 Part 1 due Tonight!

Apr 2

Cache Profiling Lab

Apr 3

Control Hazard Pitfalls [slides] [pdf]

TBD CHECK-IN 5 IN CLASS

Apr 6

Strategies to Handle Branches [slides] [pdf]

TBD

Apr 8

Branch Prediction, continued [slides] [pdf]

TBD

Apr 9

Branch Prediction Lab

Apr 10

Speculative Execution Attacks (Part 1) [slides] [pdf]

TBD HW3 Part 2 due Tonight!

Apr 13

Speculative Execution Attacks (Part 2) [slides] [pdf]

TBD HW4 released

Apr 15

Out of Order Execution (Part 1) [slides] [pdf]

TBD

Apr 16

Paranoid Processor Assignment Gear-Up

Apr 17

[Advanced Instruction Level Parallelism]

TBD HW4 Part 1 due Tonight!

Modern Computer Architectures

Apr 20

[Multicore Architectures]

TBD HW4 Released

Apr 22

[More Multicore Architectures]

TBD

Apr 23

[Ahmdahl’s Law Lab]

Apr 24

[A (Very Brief) Overview of GPUs]

TBD HW4 Part 2 due Tonight!

Apr 27

[GPUs cont.]

TBD

Apr 29

[Green Computing]

Apr 30

Lab: TBD

May 1

[Topics in Computer Architecture]

TBD

M4y 4

[Topics in Architecture Security]

TBD HW4 Part 3 due Tonight!

May 6

[Course Summary]

TBD