Preliminary calendar, subject to change!

Calendar

The Hardware Software Interface

Aug 25

Intro & What is Computer Architecture?: Syllabus

Aug 27

No Lab(re-)Introducing the HW-SW Interface: H&P 1.3, 1.9

Aug 29

Data Representations & Assembly: H&P A.1, A.2

Sept 1

Labor Day, no class!

Sept 3

Designing an Assembly Instruction: S&L 1.2

Assembly Lab

Sept 5

Assembly Design, cont.: H&P A.4, A.7 Check-In 1 in class

Sept 8

RISC v CISC: TCftRISC HW1 Released

Last Day to Add Course!

Basic Processor Design

Sept 10

Hardware Principles: TBD

Processor Emulator Gear-Up Lab

Sept 12

Building a Basic Processor (Part 1): TBD

Sept 15

Building a Basic Processor (Part 2): TBD

Sept 17

Pipelining: TBD

Pipelining Lab

Sept 19

Building a Pipelined CPU: TBD Check-In 2 in class

Sept 22

Pipelined Processor (Part 2): TBD

Sept 24

Pipeline Pitfalls and Hazards: TBD

Intro to gem5 Lab

Sept 26

Managing Hazards: TBD

Sept 29

Introducing Processor Control: TBD

Memory Hierarchy

Oct 1

Memory Hierarchy Overview: TBD HW1 due HW2 released

Cache Assignment Gear-Up Lab

Oct 3

Revisiting Locality: TBD Check-In 3 in class

Oct 6

Associativity: TBD

Oct 8

Associativity Trade-Offs: TBD

Cache Performance Lab

Oct 10

Cache Coherence: TBD

Oct 13

Fall Break, no class

Oct 15

Coherence, continued: TBD HW2 Due HW3 Released

ISA Leakage Gear-Up Lab

Tomorrow is the last day to drop course!

Oct 17

Shared Caches: TBD Check-In 4 In-class

Oct 20

Cache Security and Mitigations: TBD

Calendar

The Hardware Software Interface

Basic Processor Design

Memory Hierarchy

Advanced Processing

Modern Computer Architectures